Typically, an amount of idle time, known as a “bubble”, occurs on the data interface of a memory device when switching from a write transfer to a read transfer, also known as “W-R turnaround bubble” time. This idle time generally occurs from resource conflicts within the memory device and/or device operating constraints.
Memory device resource conflicts may consist of: 1) shared I/O pins or circuitry between read and write operations, for example bidirectional pins, 2) shared data paths between read and write operations, for example input/output paths, shifters, column I/O amplifiers and bit lines, and 3) shared address/control paths between read and write operations, for example a column decoder or predecoder logic. Many memory devices share resources in order to reduce incremental manufacturing costs and complexity.
Device operating constraints may include peak current or power restrictions related to customer usage requirements or memory device reliability requirements.
Memory devices have reduced W-R turnaround bubble time by providing a write buffer for buffering write data and address information. However, a single write buffer may cause a delay in a write operation allowing a read operation to occur before the desired write operation. Thus, a user may receive erroneous data that does not include the latest write data. Complex circuitry may be required in order to ensure data coherency when using a single write buffer. Also, a single write buffer may not be programmed to improve data transfer efficiency in multiple memory device configurations.
What is therefore desirable is a memory device and/or method that provides improved interconnect utilization within operating constraints at a low incremental device cost and complexity. In particular, it is desirable that the memory device reduce W-R turnaround bubble time without additional complex circuitry. The memory device should also be easily adaptable to multiple memory device system configurations. Further, it is desirable for a read and write method that allows for a 1) reduced write address buffer, 2) higher memory array utilization and, 3) reduced or simplified scheduling or data coherency logic.